RISC-V

RVA23 profile of RISC-V marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no longer optional accelerators bolted onto speculation-heavy cores. They are baseline capabilities that software can rely on.

RVA23 doesn’t force scalar execution to become deterministic. It simply makes determinism viable because the scalar side is no longer responsible for throughput. The vector unit handles the parallel work explicitly, and the scalar core becomes a coordinator that can be simple, predictable, and low‑power without sacrificing performance.

To understand why this shift matters, it helps to recall how thoroughly speculative execution came to dominate high-performance CPU design. It delivered speed, but at increasing cost—in power, complexity, verification burden, and security exposure. RVA23 does not reject speculation. Instead, it restores balance. It acknowledges that predictable, vector-driven parallelism is now a credible, mainstream path for performance growth.

Next week, Nuremberg will once again host one of the longest-running and most technically comprehensive events in the global electronics calendar. Founded in 2003, Embedded World began as a highly specialised exhibition centred on microcontrollers. Today, it is a broad industry forum welcoming silicon vendors, IP providers, toolchain companies, industrial automation specialists, robotics developers, security experts – and increasingly, edge AI players.

From automotive safety in software-defined vehicles to fault-tolerant, space-bound robotics, the embedded market has grown, too. This new breed of embedded application requires not only performance but predictability, longevity and efficiency, while mission-critical use cases demand hardware certified to meet rigorous safety and security standards. While much of the embedded market once depended on commercial off-the-shelf (COTS) components, differentiation today lies in tailoring compute to exact workload, power and lifecycle requirements. Customization is no longer the cherry on top, it’s a competitive advantage – something we’ll be exploring directly in two panel sessions next week (details at the end of this post).

The Armbian team released Armbian 26.2 today as a major update to this Debian/Ubuntu-based distribution and build framework for ARM devices, enhancing performance, security, and hardware compatibility.

Coming three months after Armbian 25.11, the Armbian 26.2 release adds support for new ARM boards and chips, including SpacemiT MusePi Pro, Radxa Rock 4D, Orangepi RV2, OrangePi 4A, Odroid M2, Lamobo R1, Khadas Mind, Orange Pi 6 Plus, Minisforum MS-R1, NuMaker-IoT-MA35D1-A1, SpacemiT MUSE Book, Friendlyelec NanoPi Zero2, DG SVR 865 Tiny, and Radxa E24C.

Armbian 26.2 also introduces board-level extension to mask Wayland desktop sessions, Cinnamon desktop builds for UEFI, GNOME desktop builds for stable targets, edge branch support to community targets, support for KDE Neon desktop builds, RISC-V Xfce desktop support, and support for Linux kernel 6.18 LTS on stable targets, while the latest Linux 6.19 kernel is now supported on the edge branch.

Canonical put out a new blog post today highlighting their RISC-V work over 2025 that included switching to the RVA23 profile baseline for Ubuntu 25.10 and moving forward. Now with RVA23-compatible RISC-V hardware coming to market this year, Canonical is talking up the RISC-V possibilities when paired with the upcoming Ubuntu 26.04 LTS release.

With Canonical having shifted Ubuntu 25.10 RISC-V requirements to RVA23, it limited the support to basically RISC-V on QEMU. But this year RVA23 compliant RISC-V SoCs are coming to market with the likes of the SpacemiT K3 and thus Canonical talking up the new possibilities for Ubuntu on RISC-V.

While many open-source enthusiasts like to flaunt RISC-V as not having the security challenges as x86_64 CPUs have seen over the past several years with various speculative execution / side-channel attacks and arguing for the benefits of an open-source ISA in stronger security, in practice it's not so clear-cut. Security researchers at Germany's CISPA Helmholtz Center for Information Security have found current RISC-V CPU implementations coming up short for their actual security.

Fabian Thomas and Lukas Gerlach of CISPA presented at FOSDEM 2026 this weekend in Brussels on RISC-V CPU security. They have been evaluating the security of RISC_V processor implementations in relation to the transient execution attacks and security problems that have given x86_64 CPUs much frustration in recent years. Unfortunately, the RISC-V situation isn't nearly as ideal and even with being a younger and cleaner ISA, there are vulnerabilities. There's also the matter of Linux kernel Spectre patches for RISC-V lagging behind and only working their way to mainline now, even though they are vulnerable too and years after Arm and x86 processors saw their Spectre mitigations land.

Similar to what has been available on Intel and AMD processors for users with the shadow stack for control-flow integrity, Linux on RISC-V is finally ready to roll-out its user-space control-flow integrity support.

After going through 23 rounds of patches, the Control Flow Integrity "CFI" for user-mode on RISC-V is approaching the mainline kernel. This security feature is for fending off ROP attacks manipulating the control flow of the user-space software to gain control. RISC-V uses the "zicfilp" instruction to enforce that all indirect calls land on a landing pad "lpad" instruction or will otherwise raise a software check exception. There are also RISC-V instructions introduced for helping ensure the return flow of software.

We’ve teamed up with the Linux Foundation to launch Porting Software to RISC-V (LFD114), a free, self-paced course for experienced engineers who need to move performance-critical software to RISC-V with confidence. Designed for professionals working close to the hardware, this advanced course focuses on real-world porting challenges across instruction sets, operating systems, and firmware.

RISC-V adoption is accelerating across artificial intelligence (AI) and machine learning (ML), embedded systems, data centers, automotive, high performance computing, and custom silicon. But organizations don’t start from scratch, they bring decades of existing platform software with them.

Keith Packard published Picolibc 1.8.11 on Monday as the newest release for his C library designed for embedded 32-bit and 64-bit platforms. Picolibc continues tacking on new CPU architecture support and other features for this project that started out as a conglomeration of the Newlib and AVR Libc C library codebases.

Picolibc 1.8.11 adds support for Qualcomm's Hexagon DSP architecture. Also on the CPU side are a number of RISC-V improvements like supporting the "-mlarge" model in Assembly code and improved RISC-V vector unit in the start-up code. Over on the ARM side is also improved ARM32 A-Profile operation in Thumb state.