RiscV

Condor Computing, a subsidiary of Andes Technology that creates licensable RISC-V cores, has a business model with parallels to Arm (the company) and SiFive. Andes formed Condor in 2023, so Condor is a relatively young player on the RISC-V scene. However, Andes does have RISC-V design experience prior to Condor’s formation with a few RISC-V cores under their belt from years past.

Condor is presenting their Cuzco core at Hot Chips 2025. This core is a heavyweight within the RISC-V scene, with wide out-of-order execution and a modern branch predictor and some new time based tricks. It’s in the same segment as high performance RISC-V designs like SiFive’s P870 and Veyron’s V1. Like those cores, Cuzco should stand head and shoulders above currently in-silicon RISC-V cores like Alibaba T-HEAD’s C910 and SiFive’s P550.

Besides being a wide out-of-order design, Cuzco uses mostly static scheduling in the backend to save power and reduce complexity. Condor calls this a “time-based” scheduling scheme. I’ll cover more on this later, but it’s important to note that this is purely an implementation detail. It doesn’t require ISA modifications or special treatment from the compiler for optimal performance.

This release for the first time officially supports the riscv64 architecture, allowing users to run Debian on 64-bit RISC-V hardware and benefit from all Debian 13 features.

The Wiki provides more details about riscv64 support in Debian.

Downloads:

• debian-13.0.0-riscv64-DVD-1.iso (torrent)

• debian-13.0.0-riscv64-netinst.iso (torrent)

As you may have heard, Ubuntu 25.10 will only run on RISC-V devices with RVA23 profile extensions, a change made to allow the distro to take full advantage of newer hardware capabilities without backwards-looking compromise.

But if you’re worried that Ubuntu’s pivot to the RISC-V RVA23 profile would leave you without hardware to run it on (since, right now, no RVA23 devices are available) you can relax a little as a slate of RVA23-compatible chips are due to launch in 2026 – and some this year.

Given the lack of hardware on sale right now, some have questioned the move by Canonical. Yet, it didn’t happen in a vacuum. Its engineers have access to development hardware and close partnerships with silicon vendors. Not on sale doesn’t mean they don’t exist.

8 High-Performance RISC-V Cores UR-CP100 (up to 2.0GHz)

• 1 Cluster (4x UR-CP100 cores) sharing 4MB, total 8MB
• System-level cache: 16MB shared by 2 cluster (8 cores)

The Most Powerful RISC-V Core in Mass Production to Date - UR-CP100 (RV64GCBHX)

• 64-bit out-of-order 4-issue superscalar microarchitecture
• SPECCPU2006 single-core INT@10.4/GHz
• SPECCPU2006 single-core FP@12/GHz
• UltraRISC proprietary high-performance "X" instruction set extension

Compliant with RISC-V International Foundation Standards

• Fully Compliant with RVA22
• Compliant with RVA23* (excluding "V" extension)

Supports DDR4 Memory Stick, Up to 64GB

• Compatible with standard PC-grade memory stick (UDIMM)
• Supports standard DDR4 JEDEC JESD79-4A protocol
• Supports maximum speed of 3200MT/s
• Supports ECC

Supports UEFI Boot

• Supports ACPI, CPPC, SMBIOS
• Standardized boot support
• Native ISO file mounting
• More flexible boot options
• Enhanced security

Supports Commodity NVMe SSDs (PCIe Gen4 4-lane)

Supports High-Speed USB3 5Gbps

Onboard Full-Size PCIe Connector with PCIe Gen4 16-lane

• https://bugs.launchpad.net/ubuntu/+source/ubuntu-release-upgrader/+bug/2111715
• https://www.omgubuntu.co.uk/2025/06/ubuntu-riscv-rva23-support
• https://9to5linux.com/canonical-plans-for-a-fully-functional-desktop-session-on-risc-v-with-ubuntu-25-10

cross-posted from: https://lemmy.world/post/32690684

Ever wondered how the brain of your computer works? This guide will take you from knowing nothing about processor design to having Tiny Vedas, a complete, open-source RISC-V processor running on your machine.

In this course, we'll design and implement a RISC-V processor. It's going to be a small processor, but it will allow us to see 90% of computer architecture concepts.

Important disclaimer: This course is not meant to be a comprehensive guide to RISC-V or processor design. It's intended to give you a quick and fast track to building a RISC-V processor from the ground up.

No prerequisites required - this course is targeted to people straight out of high school.