RISC-V

BayLibre is proud to announce a successful collaboration with SpacemiT to enable initial functionalities of Android 16 on the SpacemiT K1 (RISC-V RVA22 + RVV 1.0) System-on-Chip (SOC). This achievement marks a significant step toward validating and accelerating Android enablement on high-end RISC-V platforms.

The main objective of this project was to validate the feasibility of porting modern Android to recent, high-performance RISC-V platforms. Furthermore, this work serves as crucial preparation for Android enablement on upcoming RISC-V profile RVA23 SOCs, as much of the effort and code will be directly reusable.

Built for Rapid Upstream Delivery

Rolling releases with upstream tracking bring new RISC-V features and fixes to you sooner—less waiting, less rework.

Built for RISC-V Developers

Stay close to upstream to reduce backports and forks. Easier reproduction, faster debugging, smoother upstream contributions.

Built for Early Validation

Surfaces firmware, platform semantics, and Linux interoperability issues early—so vendors fix faster, reduce divergence, and reach mainstream OS compatibility sooner.

This is formal specification of the RISC-V architecture, written in Sail.

The model specifies assembly language formats of the instructions, the corresponding encoders and decoders, and the instruction semantics. A reading guide to the model is provided in the doc/ subdirectory, along with a guide on how to add a new extension to the model.

The highlight of this release is substantially improved performance on Linux boot after a fix to the handling of superpages in the TLB.

This release adds 13 new extensions; all mandatory extensions for RVAU23 are now supported.

Several configuration parameters have been added, along with new command line options. The model implements a simple external interrupt generator, and the wait duration of instructions like WFI can be specified. The handling of misaligned accesses can bespecified at a more granular level.

RVA23 profile of RISC-V marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no longer optional accelerators bolted onto speculation-heavy cores. They are baseline capabilities that software can rely on.

RVA23 doesn’t force scalar execution to become deterministic. It simply makes determinism viable because the scalar side is no longer responsible for throughput. The vector unit handles the parallel work explicitly, and the scalar core becomes a coordinator that can be simple, predictable, and low‑power without sacrificing performance.

To understand why this shift matters, it helps to recall how thoroughly speculative execution came to dominate high-performance CPU design. It delivered speed, but at increasing cost—in power, complexity, verification burden, and security exposure. RVA23 does not reject speculation. Instead, it restores balance. It acknowledges that predictable, vector-driven parallelism is now a credible, mainstream path for performance growth.

Next week, Nuremberg will once again host one of the longest-running and most technically comprehensive events in the global electronics calendar. Founded in 2003, Embedded World began as a highly specialised exhibition centred on microcontrollers. Today, it is a broad industry forum welcoming silicon vendors, IP providers, toolchain companies, industrial automation specialists, robotics developers, security experts – and increasingly, edge AI players.

From automotive safety in software-defined vehicles to fault-tolerant, space-bound robotics, the embedded market has grown, too. This new breed of embedded application requires not only performance but predictability, longevity and efficiency, while mission-critical use cases demand hardware certified to meet rigorous safety and security standards. While much of the embedded market once depended on commercial off-the-shelf (COTS) components, differentiation today lies in tailoring compute to exact workload, power and lifecycle requirements. Customization is no longer the cherry on top, it’s a competitive advantage – something we’ll be exploring directly in two panel sessions next week (details at the end of this post).

The Armbian team released Armbian 26.2 today as a major update to this Debian/Ubuntu-based distribution and build framework for ARM devices, enhancing performance, security, and hardware compatibility.

Coming three months after Armbian 25.11, the Armbian 26.2 release adds support for new ARM boards and chips, including SpacemiT MusePi Pro, Radxa Rock 4D, Orangepi RV2, OrangePi 4A, Odroid M2, Lamobo R1, Khadas Mind, Orange Pi 6 Plus, Minisforum MS-R1, NuMaker-IoT-MA35D1-A1, SpacemiT MUSE Book, Friendlyelec NanoPi Zero2, DG SVR 865 Tiny, and Radxa E24C.

Armbian 26.2 also introduces board-level extension to mask Wayland desktop sessions, Cinnamon desktop builds for UEFI, GNOME desktop builds for stable targets, edge branch support to community targets, support for KDE Neon desktop builds, RISC-V Xfce desktop support, and support for Linux kernel 6.18 LTS on stable targets, while the latest Linux 6.19 kernel is now supported on the edge branch.

Canonical put out a new blog post today highlighting their RISC-V work over 2025 that included switching to the RVA23 profile baseline for Ubuntu 25.10 and moving forward. Now with RVA23-compatible RISC-V hardware coming to market this year, Canonical is talking up the RISC-V possibilities when paired with the upcoming Ubuntu 26.04 LTS release.

With Canonical having shifted Ubuntu 25.10 RISC-V requirements to RVA23, it limited the support to basically RISC-V on QEMU. But this year RVA23 compliant RISC-V SoCs are coming to market with the likes of the SpacemiT K3 and thus Canonical talking up the new possibilities for Ubuntu on RISC-V.